So far we've measured two out of the 4 lines when using I2S. Strictly speaking, I2S only has 3 lines, but the Master Clock line is required by the DAC and some component generates the master clock.
So we've measured MCK, LRCK and now we measure BCK. The data line cannot be measured because it varies with the data and it is a bit pattern corresponding to the data. So with these 3 measurements, we can characterized the I2S interface.
For 44.1KHz material, we measured 2.8236 MHz. What does this mean? 28236/441=64.0. The BCK is running at 64 times the sampling rate or 64fs. This means that the device sends 32-bit words per channel (yes 32 bits of data per channel).
BCK can be 32fs (16 bit -16-bitx2), 48fs (24-bit per channel) or 64fs (32-bit per channel as it is in our case). DACs data sheet specify the word length it can accept, but since the send and receive bit depth do not have to match, words are either padded or truncated if there is a mismatch.
If the Transmitter is sending 32 bits per channel to a device with only 24 bits of internal precision, the Receiver may simply ignore the extra bits of precision by not storing the bits past the 24th bit. Likewise, if the Transmitter is sending 16 bits per channel to a Receiving device with 24 bits of precision, the receiver will simply Zero-fill the missing bits. This feature makes it possible to mix and match components of varying precision without reconfiguration.This is possible because data is transmitted MSB first.