- Support for 4x20 LCD Display and large number display
- Brightness and contrast adjustment with remote
- (OPUS/Wolfson WM8741) DAC volume control: remote and rotary encoder
- (OPUS/Wolfson WM8741) DAC random filter selection 1 to 5 with remote
- (OPUS/Wolfson WM8741) DAC upsampling selection (L, M, H -this is the OSR setting)
- I2C level shifting (5V to 3.3V)
- Optimized power-up sequence

Saturday, February 6, 2010

Programming the WM8804

I'm going to attempt to use the WM8804 SPDIF receiver in software mode. A quick look at the datasheet shows that there are 30 registers to program!. I've done an extensive search in the internet and there are no projects involving using this part in software mode. In fact, it seems it is not very easy to program.

But first lets explore this device in a bit more detail.

According to the manufacturer, the WM8804 has the lowest intrinsic jitter of any commercial spdif receiver. In addition, it provides large immunity against incoming jitter.

Lets explore why the WM8804 is immune to incoming jitter.

Conventional spdif receivers utilize a PLL to lock into the signal. Devices such as the very popular CS8412/14/16 operate this way. A PLL generates an initial clock with a VCO (voltage controlled oscillator) and compares the phase of that clock with an incoming clock. The error in phase results in a voltage that is feed back to the VCO until the output clock "locks" unto the input clock. According to an AES paper:
Popular S/PDIF receiver chips like the Yamaha YM3623B and Crystal CS8412 are NOT crystal controlled but rather recover the necessary clock from internal Phase Locked Loops (PLL) locked onto the incoming data stream. The simple two pin can crystals often seen directly attached to '3623's and '8412's are optional. The 3623 uses the crystal clock to quickly lock onto the S/PDIF signal. The 8412 uses the crystal clock to determine and display the sample rate and jitter level of the S/PDIF signal. Both parts ignore the local crystal clock once locked onto the S/PDIF signal.
Higher end parts will use a sample rate converter to further clean the jitter. Both TI and Cirrus have spdif receivers with built in ASRCs It is noted that the use of ASRC is controversial in high end audio (there are camps on both sides)

According to Wolfson in their white paper:
The goal here is to synchronize a clock generated from a PLL and high quality oscillator to incoming S/PDIF data stream. This is different to usual approach of using a PLL to recover a clock from the S/PDIF data stream, which inherently has to track the jitter to maintain lock.
The white paper gives the technical details, but suffice to say that it is essentially a PLL followed by a re-clocker (not a sample rate converter) with a time based derived from the crystal. I have a post comparing the difference between re-clocking and sample rate conversion here.

Measurements by Wolfson shows the WM8804 compared with another commercial part

The following picture shows the jitter performance of the WM8804 with incoming signal having 5UI of jitter injected in the input sdif signal (5UI is 5x163nsec for 48K sample frequency). Result: 51.7 psec (period jitter RMS) which is the same as the spec'ed intrinsic jitter of the device (50 psec)

The following picture shows the jitter performance of a competitive device spec'ed with 150 psec of intrinsic jitter. The result is 334psec (period jitter RMS)

To be fair, 5UI of jitter which translates into 800 nsec which is a HUGE amount of jitter. The lowly Apple Airport Express was measured by Stereophile to have a "respectably low 258ps of jitter" in the spdif output. Thus in real life, I think the relevant measure is intrinsic jitter in which the Wolfson part excels at 50 psec

Here is the WM8804 Implementation by TwistedPearAudio:


leeperry said...

hi, thanks for the great informations! but do you still have wolfson white paper? it's a 404 now :(

The Lazy Engineer said...

Fixed the link to the white paper

Anonymous said...

how does the SPDIF output signal from the WM8804 TX0 pin looks like?
Is it 0 to DvDD or 0 to 1 V? Because i saw a 210R to 110R voltage divider in the application note.


Anonymous said...

I don't remember. Because of the voltage divider and because the maximum is the 3.3V digital supply, I would say 1V

Anonymous said...


Can you explain how you have made measurements?
What measuring instruments do you use?

Best Regards

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